1. Field of the Invention
The disclosure relates to semiconductor devices, and more particularly, to semiconductor devices having dual capping layer patterns and methods of manufacturing the same.
2. Description of the Related Art
In recent years, there has been increased interest in forming at the same time contact holes which penetrate at least one interlayer insulating layer in a cell array region and a peripheral circuit region. In forming the contact hole, it is important to reduce the number of masks used in a semiconductor fabrication process. So, a gate line of a multi layer structure should be optimized. This is because among the contact holes one which is formed on the gate line should be formed in consideration of an etching selectivity ratio that is different from the interlayer insulating layer. That is, a stable profile should be obtained for a contact resistance of the contact hole. A conventional semiconductor device having the contact hole is explained as follows.
FIG. 1 is a cross-sectional diagram illustrating a conventional semiconductor device.
Referring to FIG. 1, a trench separating layer 10 and a gate insulating layer 14 are formed on a semiconductor substrate 1 having a cell array region B and a peripheral circuit region C. A plurality of word line patterns 30 and at least one gate pattern 30-1 are formed on the gate insulating layer 14 in cell array region B and the gate insulating layer 14 in the peripheral circuit region C, respectively. Each of the word line patterns 30 includes a word line 16 and a word line capping layer 18. The gate pattern 30-1 includes a gate electrode 16-1 and a gate capping layer pattern 18-1. The word line 16 and the gate electrode 16-1 are formed of a doped polysilicon layer. The word line capping layer pattern 18 and the gate capping layer pattern 18-1 are formed of a nitride layer. N− low concentration regions 20 are formed on the semiconductor substrate 1 using the word line pattern 30 and the gate pattern 30-1 as a mask. Gate spacers 22 are formed on side walls of the word line pattern 30 and the gate pattern 30-1. The gate spacer 22 is formed of a nitride layer. Also, N+ high concentration regions may be further formed in the semiconductor substrate 1 of the peripheral circuit region by using the gate patterns 30-1 and the gate spacers 22 as a mask, thereby forming a light doped drain (LDD) structure together with the N− low concentration regions 20. A pad interlayer insulating layer 32 is formed over the semiconductor substrate 1 having the gate spacer 22. The pad interlayer insulating layer 32 is formed of an oxide layer. Pad contact holes 40, 45, and 50 are formed in portions of the pad interlayer insulating layer 32 between the word line patterns 18. Landing pads 52, 54, and 56 are formed to fill the pad contact holes 40, 45, and 50, respectively. A bit line interlayer insulating layer 58 is formed over the semiconductor substrate 1 having the landing pads 52, 54, and 56. The bit line interlayer insulating layer 58 is formed of an oxide layer. The bit line interlayer insulating layer 58, the pad interlayer insulating layer 32, and the gate capping pattern 18-1 are sequentially patterned to form a cell contact hole 60 and a peripheral circuit contact hole 65 in the cell array region B and the peripheral circuit region C, respectively. The cell contact hole 60 is formed to expose one selected from the landing pads 52, 54, and 56, and the peripheral circuit contact hole 65 exposes a portion of the gate electrode 16-1. Then, bit lines 70 and 70-1 are formed to fill the cell contact hole 60 and the peripheral circuit contact hole 65, respectively.
In the peripheral circuit region, however, the pad interlayer insulating layer 32 and the bit line interlayer insulating layer 58 have an etching selectivity ratio different from the gate capping layer pattern 18-1. This means that the pad interlayer insulating layer 32 and the bit line interlayer insulating layer 58 differ from the gate capping layer pattern 18-1 in etching amount per a unit time. Therefore, a profile of the peripheral circuit contact hole 65 formed on the gate capping layer pattern 18-1 is different from that of the cell contact hole 60. As a result, since a profile of the peripheral circuit contact hole 65 is not uniform, a process tolerance for the dry etching becomes narrow, and the performance of the semiconductor device deteriorates.
Also, the more a design rule is reduced, the more closely the semiconductor device approaches the limitations of the photolithography process used in forming the pad contact holes 40, 45, and 50. That is, since a gap “A” between the pad contact holes 40, 45, and 50 is reduced to meet a reduced design rule, a short circuit may occur between the landing pads 52, 54, and 56. This results in a problem that an overlapping width W1 between the pad contact holes 40, 45, and 50 and the word line capping layer pattern 18 should be small.
On the other hand, U.S. Pat. No. 6,423,627 to Carter et al. (the '627 patent) discloses a method for forming memory array and periphery contacts using the same mask.
According to the '627 patent, the method includes forming a gate insulating layer on a semiconductor substrate having a memory array region and a peripheral circuit region. A plurality of gate electrodes are formed on portions of the gate insulating layer in the memory array region, and disposable caps are formed on the gate electrodes. At least one gate electrode is formed on a portion of the gate insulating layer in the peripheral circuit region, and a disposable cap is formed on the gate electrode. The width of the gate electrode in the peripheral circuit region is greater than the width of the gate electrode in the memory array region. Spacers are formed on side walls of the gate electrodes and the disposable caps. An initial insulating layer is formed over the semiconductor substrate having the spacers. The initial insulating layer is planarized to expose the disposable caps in the memory array region and the peripheral circuit region. The disposable caps are selectively removed. A first insulating layer is formed over the semiconductor substrate having the initial insulating layer. The first insulating layer is entirely etched back. Here, in the memory array region, the initial insulating layer is exposed and at the same time the first insulating layer is filled in portions corresponding to the disposable caps. In the peripheral circuit region, inward spacers made of the first insulating layer are formed on side walls of the gate electrodes and the spacers, exposing the gate electrode. A second insulating layer is formed over the semiconductor substrate having the inward spacers. A self-aligned contact hole is formed in a region between the gate electrodes to penetrate the initial insulating layer and the second insulating layer and expose the semiconductor substrate. At the same time, a peripheral contact hole is formed in a region between the inward spacers to penetrate the second insulating layer in the peripheral circuit region and expose the gate electrode. The self-aligned contact hole and the peripheral contact hole are formed using a single mask.
However, this method may cause a removal of the disposable cap on the gate electrode and a formation of the first insulating layer on the gate electrode to burden the semiconductor fabrication process. Also, the formation of the inward spacers in the peripheral circuit region can add plasma damage resulting from the gate electrode being exposed to etching gas.